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class="nav-number">1.2.1.</span> <span class="nav-text">CPU在处理指令时，一般需要经过以下几个步骤：</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#%E5%85%B6%E4%B8%AD%EF%BC%8C"><span class="nav-number">1.2.2.</span> <span class="nav-text">其中，</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#%E5%8D%95%E5%91%A8%E6%9C%9FCPU%E6%95%B0%E6%8D%AE%E9%80%9A%E8%B7%AF%E5%92%8C%E6%8E%A7%E5%88%B6%E7%BA%BF%E8%B7%AF%E5%9B%BE%EF%BC%9A"><span class="nav-number">1.2.3.</span> <span class="nav-text">单周期CPU数据通路和控制线路图：</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E7%9B%B8%E5%85%B3%E9%83%A8%E4%BB%B6%E5%8F%8A%E5%BC%95%E8%84%9A%E8%AF%B4%E6%98%8E%EF%BC%9A"><span class="nav-number">1.2.3.1.</span> <span class="nav-text">相关部件及引脚说明：</span></a></li></ol></li></ol></li><li class="nav-item nav-level-3"><a class="nav-link" href="#%E5%AE%9E%E9%AA%8C%E8%BF%87%E7%A8%8B%E4%B8%8E%E7%BB%93%E6%9E%9C"><span class="nav-number">1.3.</span> <span class="nav-text">实验过程与结果</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E5%AE%8C%E6%88%90%E6%8E%A7%E5%88%B6%E4%BF%A1%E5%8F%B7%E4%B8%8E%E7%9B%B8%E5%AF%B9%E5%BA%94%E6%8C%87%E4%BB%A4%E4%B9%8B%E9%97%B4%E7%9B%B8%E4%BA%92%E5%85%B3%E7%B3%BB%E7%9A%84%E8%A1%A8%E6%A0%BC"><span class="nav-number">1.3.0.1.</span> <span class="nav-text">完成控制信号与相对应指令之间相互关系的表格</span></a></li><li class="nav-item nav-level-5"><a class="nav-link" href="#CPU%E6%A8%A1%E5%9D%97%E5%88%92%E5%88%86%E4%B8%8E%E5%AE%9E%E7%8E%B0"><span class="nav-number">1.3.0.2.</span> <span class="nav-text">CPU模块划分与实现</span></a></li></ol></li><li class="nav-item nav-level-4"><a class="nav-link" href="#pcAdd"><span class="nav-number">1.3.1.</span> <span class="nav-text">pcAdd</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#PC"><span class="nav-number">1.3.2.</span> <span class="nav-text">PC</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#InsMEM"><span class="nav-number">1.3.3.</span> <span class="nav-text">InsMEM</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#InstructionCut"><span class="nav-number">1.3.4.</span> <span class="nav-text">InstructionCut</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#ControlUnit"><span class="nav-number">1.3.5.</span> <span class="nav-text">ControlUnit</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#RegisterFile"><span class="nav-number">1.3.6.</span> <span class="nav-text">RegisterFile</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#ALU"><span class="nav-number">1.3.7.</span> <span class="nav-text">ALU</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#DataMEM"><span class="nav-number">1.3.8.</span> <span class="nav-text">DataMEM</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#SignZeroExtend"><span class="nav-number">1.3.9.</span> <span class="nav-text">SignZeroExtend</span></a></li><li class="nav-item nav-level-4"><a class="nav-link" href="#%E9%A1%B6%E5%B1%82%E6%A8%A1%E5%9D%97%EF%BC%9ASingleCycleCPU"><span class="nav-number">1.3.10.</span> <span class="nav-text">顶层模块：SingleCycleCPU</span></a></li></ol></li><li class="nav-item nav-level-3"><a class="nav-link" href="#CPU%E6%AD%A3%E7%A1%AE%E6%80%A7%E7%9A%84%E9%AA%8C%E8%AF%81"><span class="nav-number">1.4.</span> <span class="nav-text">CPU正确性的验证</span></a><ol class="nav-child"><li class="nav-item nav-level-4"><a class="nav-link" href="#%E4%BB%BF%E7%9C%9F%E7%A8%8B%E5%BA%8F%EF%BC%9A"><span class="nav-number">1.4.1.</span> <span class="nav-text">仿真程序：</span></a><ol class="nav-child"><li class="nav-item nav-level-5"><a class="nav-link" href="#%E7%A8%8B%E5%BA%8F%E4%BB%A3%E7%A0%81%E6%B5%8B%E8%AF%95"><span class="nav-number">1.4.1.1.</span> <span class="nav-text">程序代码测试</span></a></li></ol></li><li class="nav-item nav-level-4"><a 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          单周期 CPU 设计与实现
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        <h2 id="单周期CPU设计与实现"><a href="#单周期CPU设计与实现" class="headerlink" title="单周期CPU设计与实现"></a>单周期CPU设计与实现</h2><p><img src="https://cdn.jsdelivr.net/gh/PDPENG/jason-storage/blog-img/20220515095544.png"></p>
<h3 id="实验内容：学校资料"><a href="#实验内容：学校资料" class="headerlink" title="实验内容：学校资料"></a>实验内容：<code>学校资料</code></h3><p>设计一个单周期CPU，该CPU至少能实现以下指令功能操作。指令与格式如下：</p>
<span id="more"></span>

<p>=&#x3D;&gt; 算术运算指令<br>1. add rd , rs, rt （说明：以助记符表示，是汇编指令；以代码表示，是机器指令）</p>
<table>
<thead>
<tr>
<th>000000</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">rd(5位)</th>
<th>reserved</th>
</tr>
</thead>
</table>
<p>功能：rd←rs + rt。reserved为预留部分，即未用，一般填“0”。<br>2. addi rt , rs ,immediate</p>
<table>
<thead>
<tr>
<th>000001</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：rt←rs + (sign-extend)immediate；immediate符号扩展再参加“加”运算。<br>3. sub rd , rs , rt</p>
<table>
<thead>
<tr>
<th>000000</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">rd(5位)</th>
<th>reserved</th>
</tr>
</thead>
</table>
<p>功能：rd←rs - rt<br>=&#x3D;&gt; 逻辑运算指令<br>4. ori rt , rs ,immediate</p>
<table>
<thead>
<tr>
<th>010000</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：rt←rs | (zero-extend)immediate；immediate做“0”扩展再参加“或”运算。<br>5. and rd , rs , rt</p>
<table>
<thead>
<tr>
<th>010001</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">rd(5位)</th>
<th>reserved</th>
</tr>
</thead>
</table>
<p>功能：rd←rs &amp; rt；逻辑与运算。<br>6. or rd , rs , rt</p>
<table>
<thead>
<tr>
<th>010010</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">rd(5位)</th>
<th>reserved</th>
</tr>
</thead>
</table>
<p>功能：rd←rs | rt；逻辑或运算。</p>
<p>=&#x3D;&gt;移位指令<br>7. sll rd, rt,sa</p>
<table>
<thead>
<tr>
<th>011000</th>
<th align="center">未用</th>
<th align="right">rt(5位)</th>
<th align="right">rd(5位)</th>
<th>sa</th>
<th>reserved</th>
</tr>
</thead>
</table>
<p>功能：rd&lt;－rt&lt;&lt;(zero-extend)sa，左移sa位 ，(zero-extend)sa</p>
<p>=&#x3D;&gt;比较指令<br>8. slti rt, rs,immediate 带符号</p>
<table>
<thead>
<tr>
<th>011011</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：if (rs &lt;(sign-extend)immediate) rt &#x3D;1 else rt&#x3D;0， 具体请看表2 ALU运算功能表，带符号</p>
<p>=&#x3D;&gt; 存储器读&#x2F;写指令<br>9. sw rt ,immediate(rs) 写存储器</p>
<table>
<thead>
<tr>
<th>100110</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：memory[rs+ (sign-extend)immediate]←rt；immediate符号扩展再相加。即将rt寄存器的内容保存到rs寄存器内容和立即数符号扩展后的数相加作为地址的内存单元中。<br>10. lw rt , immediate(rs) 读存储器</p>
<table>
<thead>
<tr>
<th>100111</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：rt ← memory[rs + (sign-extend)immediate]；immediate符号扩展再相加。<br>即读取rs寄存器内容和立即数符号扩展后的数相加作为地址的内存单元中的数，然后保存到rt寄存器中。</p>
<p>=&#x3D;&gt; 分支指令<br>11. beq rs,rt,immediate</p>
<table>
<thead>
<tr>
<th>110000</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：if(rs&#x3D;rt) pc←pc + 4 + (sign-extend)immediate &lt;&lt;2 else pc ←pc + 4<br>特别说明：immediate是从PC+4地址开始和转移到的指令之间指令条数。immediate符号扩展之后左移2位再相加。为什么要左移2位？由于跳转到的指令地址肯定是4的倍数（每条指令占4个字节），最低两位是“00”，因此将immediate放进指令码中的时候，是右移了2位的，也就是以上说的“指令之间指令条数”。<br>12. bne rs,rt,immediate</p>
<table>
<thead>
<tr>
<th>110001</th>
<th align="center">rs(5位)</th>
<th align="right">rt(5位)</th>
<th align="right">immediate(16位)</th>
</tr>
</thead>
</table>
<p>功能：if(rs!&#x3D;rt) pc←pc + 4 + (sign-extend)immediate &lt;&lt;2 else pc ←pc + 4<br>特别说明：与beq不同点是，不等时转移，相等时顺序执行。</p>
<p>=&#x3D;&gt;跳转指令<br>13. j addr</p>
<table>
<thead>
<tr>
<th>111000</th>
<th align="center">addr[27…2]</th>
</tr>
</thead>
</table>
<p>功能：pc &lt;－{(pc+4)[31..28],addr[27..2],2{0}}，无条件跳转。<br>说明：由于MIPS32的指令代码长度占4个字节，所以指令地址二进制数最低2位均为0，将指令地址放进指令代码中时，可省掉！这样，除了最高6位操作码外，还有26位可用于存放地址，事实上，可存放28位地址了，剩下最高4位由pc+4最高4位拼接上。<br>=&#x3D;&gt; 停机指令<br>14. halt</p>
<table>
<thead>
<tr>
<th>111111</th>
<th align="center">00000000000000000000000000(26位)</th>
</tr>
</thead>
</table>
<p>功能：停机；不改变PC的值，PC保持不变。</p>
<h3 id="实验原理："><a href="#实验原理：" class="headerlink" title="实验原理："></a>实验原理：</h3><p>单周期CPU指的是一条指令的执行在一个时钟周期内完成，然后开始下一条指令的执行，即一条指令用一个时钟周期完成。电平从低到高变化的瞬间称为时钟上升沿，两个相邻时钟上升沿之间的时间间隔称为一个时钟周期。时钟周期一般也称振荡周期（如果晶振的输出没有经过分频就直接作为CPU的工作时钟，则时钟周期就等于振荡周期。若振荡周期经二分频后形成时钟脉冲信号作为CPU的工作时钟，这样，时钟周期就是振荡周期的两倍。）</p>
<h4 id="CPU在处理指令时，一般需要经过以下几个步骤："><a href="#CPU在处理指令时，一般需要经过以下几个步骤：" class="headerlink" title="CPU在处理指令时，一般需要经过以下几个步骤："></a>CPU在处理指令时，一般需要经过以下几个步骤：</h4><ul>
<li>取指令(IF)：根据程序计数器PC中的指令地址，从存储器中取出一条指令，同时，PC根据指令字长度自动递增产生下一条指令所需要的指令地址，但遇到“地址转移”指令时，则控制器把“转移地址”送入PC，当然得到的“地址”需要做些变换才送入PC。</li>
<li>指令译码(ID)：对取指令操作中得到的指令进行分析并译码，确定这条指令需要完成的操作，从而产生相应的操作控制信号，用于驱动执行状态中的各种操作。</li>
<li>指令执行(EXE)：根据指令译码得到的操作控制信号，具体地执行指令动作，然后转移到结果写回状态。</li>
<li>存储器访问(MEM)：所有需要访问存储器的操作都将在这个步骤中执行，该步骤给出存储器的数据地址，把数据写入到存储器中数据地址所指定的存储单元或者从存储器中得到数据地址单元中的数据。</li>
<li>结果写回(WB)：指令执行的结果或者访问存储器中得到的数据写回相应的目的寄存器中。</li>
</ul>
<p>单周期CPU，是在一个时钟周期内完成这五个阶段的处理。</p>
<p>MIPS指令的三种格式：  </p>
<p><img src="https://cdn.jsdelivr.net/gh/PDPENG/jason-storage/blog-img/20220515095728.png"></p>
<h4 id="其中，"><a href="#其中，" class="headerlink" title="其中，"></a>其中，</h4><ul>
<li>op：为操作码；</li>
<li>rs：只读。为第1个源操作数寄存器，寄存器地址（编号）是00000~11111，00~1F；</li>
<li>rt：可读可写。为第2个源操作数寄存器，或目的操作数寄存器，寄存器地址（同上）；</li>
<li>rd：只写。为目的操作数寄存器，寄存器地址（同上）；</li>
<li>sa：为位移量（shift amt），移位指令用于指定移多少位；</li>
<li>funct：为功能码，在寄存器类型指令中（R类型）用来指定指令的功能与操作码配合使用；</li>
<li>immediate：为16位立即数，用作无符号的逻辑操作数、有符号的算术操作数、数据加载（Load）&#x2F;数据保存（Store）指令的数据地址字节偏移量和分支指令中相对程序计数器（PC）的有符号偏移量；</li>
<li>address：为地址。</li>
</ul>
<h4 id="单周期CPU数据通路和控制线路图："><a href="#单周期CPU数据通路和控制线路图：" class="headerlink" title="单周期CPU数据通路和控制线路图："></a>单周期CPU数据通路和控制线路图：</h4><p><img src="https://cdn.jsdelivr.net/gh/PDPENG/jason-storage/blog-img/20220515095544.png"></p>
<table>
<thead>
<tr>
<th>控制信号名</th>
<th>状态“0”</th>
<th>状态“1”</th>
</tr>
</thead>
<tbody><tr>
<td>Reset</td>
<td>初始化PC为0</td>
<td>PC接收新地址</td>
</tr>
<tr>
<td>PCWre</td>
<td>PC不更改，相关指令：halt</td>
<td>PC更改，相关指令：除指令halt外</td>
</tr>
<tr>
<td>ALUSrcA</td>
<td>来自寄存器堆data1输出，相关指令：add、sub、addi、or、and、ori、beq、bne、slti、sw、lw</td>
<td>来自移位数sa，同时，进行(zero-extend)sa，即 {<!-- -->{27{0}},sa}，相关指令：sll</td>
</tr>
<tr>
<td>ALUSrcB</td>
<td>来自寄存器堆data2输出，相关指令：add、sub、or、and、sll、beq、bne</td>
<td>来自sign或zero扩展的立即数，相关指令：addi、ori、slti、sw、lw</td>
</tr>
<tr>
<td>DBDataSrc</td>
<td>来自ALU运算结果的输出，相关指令：add、addi、sub、ori、or、and、slti、sll</td>
<td>来自数据存储器（Data MEM）的输出，相关指令：lw</td>
</tr>
<tr>
<td>RegWre</td>
<td>无写寄存器组寄存器，相关指令：beq、bne、sw、halt、j</td>
<td>寄存器组写使能，相关指令：add、addi、sub、ori、or、and、slti、sll、lw</td>
</tr>
<tr>
<td>InsMemRW</td>
<td>写指令存储器</td>
<td>读指令存储器(Ins. Data)</td>
</tr>
<tr>
<td>mRD</td>
<td>输出高阻态</td>
<td>读数据存储器，相关指令：lw</td>
</tr>
<tr>
<td>mWR</td>
<td>无操作</td>
<td>写数据存储器，相关指令：sw</td>
</tr>
<tr>
<td>RegDst</td>
<td>写寄存器组寄存器的地址，来自rt字段，相关指令：addi、ori、lw、slti</td>
<td>写寄存器组寄存器的地址，来自rd字段，相关指令：add、sub、and、or、sll</td>
</tr>
<tr>
<td>ExtSel</td>
<td>(zero-extend)immediate（0扩展），相关指令：ori</td>
<td>(sign-extend)immediate（符号扩展），相关指令：addi、slti、sw、lw、beq、bne</td>
</tr>
<tr>
<td>PCSrc[1..0]</td>
<td>00：pc&lt;－pc+4，相关指令：add、addi、sub、or、ori、and、slti、sll、sw、lw、beq(zero&#x3D;0)、bne(zero&#x3D;1)；01：pc&lt;－pc+4+(sign-extend)immediate，相关指令：beq(zero&#x3D;1)、bne(zero&#x3D;0)；10：pc&lt;－{(pc+4)[31:28],addr[27:2],2{0}}，相关指令：j；11：未用</td>
<td>-</td>
</tr>
<tr>
<td>ALUOp[2..0]</td>
<td>ALU 8种运算功能选择(000-111)，看功能表</td>
<td></td>
</tr>
</tbody></table>
<h5 id="相关部件及引脚说明："><a href="#相关部件及引脚说明：" class="headerlink" title="相关部件及引脚说明："></a><code>相关部件及引脚说明：</code></h5><ul>
<li>Instruction Memory：指令存储器，</li>
<li>Iaddr，指令存储器地址输入端口</li>
<li>IDataIn，指令存储器数据输入端口（指令代码输入端口）</li>
<li>IDataOut，指令存储器数据输出端口（指令代码输出端口）</li>
<li>RW，指令存储器读写控制信号，为0写，为1读</li>
<li>Data Memory：数据存储器，</li>
<li>Daddr，数据存储器地址输入端口</li>
<li>DataIn，数据存储器数据输入端口</li>
<li>DataOut，数据存储器数据输出端口</li>
<li>&#x2F;RD，数据存储器读控制信号，为0读</li>
<li>&#x2F;WR，数据存储器写控制信号，为0写</li>
<li>Register File：寄存器组</li>
<li>Read Reg1，rs寄存器地址输入端口</li>
<li>Read Reg2，rt寄存器地址输入端口</li>
<li>Write Reg，将数据写入的寄存器端口，其地址来源rt或rd字段</li>
<li>Write Data，写入寄存器的数据输入端口</li>
<li>Read Data1，rs寄存器数据输出端口</li>
<li>Read Data2，rt寄存器数据输出端口</li>
<li>WE，写使能信号，为1时，在时钟边沿触发写入</li>
<li>ALU： 算术逻辑单元</li>
<li>result，ALU运算结果</li>
<li>zero，运算结果标志，结果为0，则zero&#x3D;1；否则zero&#x3D;0</li>
</ul>
<blockquote>
<p><strong>表2 ALU运算功能表</strong></p>
</blockquote>
<table>
<thead>
<tr>
<th><strong>ALUOp[2:0]</strong></th>
<th><strong>功能</strong></th>
<th><strong>描述</strong></th>
</tr>
</thead>
<tbody><tr>
<td><strong>000</strong></td>
<td><strong>Y &#x3D; A + B</strong></td>
<td><strong>加</strong></td>
</tr>
<tr>
<td><strong>001</strong></td>
<td><strong>Y &#x3D; A – B</strong></td>
<td><strong>减</strong></td>
</tr>
<tr>
<td><strong>010</strong></td>
<td><strong>Y &#x3D; B &lt;&lt; A</strong></td>
<td><strong>B左移A位</strong></td>
</tr>
<tr>
<td><strong>011</strong></td>
<td><strong>Y &#x3D; A ∨ B</strong></td>
<td><strong>或</strong></td>
</tr>
<tr>
<td><strong>100</strong></td>
<td><strong>Y &#x3D; A ∧ B</strong></td>
<td><strong>与</strong></td>
</tr>
<tr>
<td><strong>101</strong></td>
<td><strong>Y &#x3D;（A &lt; B）? 1: 0</strong></td>
<td><strong>比较A与B 不带符号</strong></td>
</tr>
<tr>
<td><strong>110</strong></td>
<td></td>
<td><strong>比较A与B 带符号</strong></td>
</tr>
<tr>
<td><strong>111</strong></td>
<td><strong>Y &#x3D; A ⊕ B</strong></td>
<td><strong>异或</strong></td>
</tr>
</tbody></table>
<h3 id="实验过程与结果"><a href="#实验过程与结果" class="headerlink" title="实验过程与结果"></a>实验过程与结果</h3><blockquote>
<p><strong>设计思路以及流程：</strong></p>
</blockquote>
<h5 id="完成控制信号与相对应指令之间相互关系的表格"><a href="#完成控制信号与相对应指令之间相互关系的表格" class="headerlink" title="完成控制信号与相对应指令之间相互关系的表格"></a>完成控制信号与相对应指令之间相互关系的表格</h5><blockquote>
<p>表3是依据表1控制信号的作用以及表2 ALU运算功能表完成的，某些指令无需用到部分模块，则相对应模块的使能控制信号与其无关。例如，对于跳转指令而言，其无需对数据寄存器进行读写操作，则数据寄存器相关的控制信号mRD，mWR设为0，防止修改里面的数据。部分指令执行不需要所有的模块都参与，故有些模块的控制信号与其没有直接关系，为了防止出现一些不必要的错误，统一将指令相对应的无关的使能控制信号默认设置为低电平(0)，无需ALU运算的(例如跳转指令)默认将其操作变成(000)。**</p>
</blockquote>
<p><strong>表3 控制信号与相对应指令之间的相互关系</strong></p>
<table>
<thead>
<tr>
<th><strong>指 令</strong></th>
<th><strong>控制信号量</strong></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td></td>
<td><strong>PCWre</strong></td>
<td><strong>ExtSel</strong></td>
<td><strong>InsMemRW</strong></td>
<td><strong>RegDst</strong></td>
<td><strong>RegWre</strong></td>
<td><strong>ALUSrcA</strong></td>
<td><strong>ALUSrcB</strong></td>
<td><strong>PCSrc(zero:0&#x2F;1)</strong></td>
<td><strong>ALUOp</strong></td>
<td><strong>mRD</strong></td>
<td><strong>mWR</strong></td>
<td><strong>DBDataSrc</strong></td>
</tr>
<tr>
<td><strong>addi</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>00</strong></td>
<td><strong>000</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>ori</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>00</strong></td>
<td><strong>011</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>add</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>00</strong></td>
<td><strong>000</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>sub</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>00</strong></td>
<td><strong>001</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>and</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>00</strong></td>
<td><strong>100</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>or</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>00</strong></td>
<td><strong>011</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>sll</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>00</strong></td>
<td><strong>010</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>bne</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>X</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>01&#x2F; 00</strong></td>
<td><strong>001</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>slti</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>00</strong></td>
<td><strong>101</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>beq</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>X</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>00 &#x2F; 01</strong></td>
<td><strong>001</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>sw</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>X</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>00</strong></td>
<td><strong>000</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>lw</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>00</strong></td>
<td><strong>000</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
</tr>
<tr>
<td><strong>j</strong></td>
<td><strong>1</strong></td>
<td><strong>0</strong></td>
<td><strong>1</strong></td>
<td><strong>X</strong></td>
<td><strong>0</strong></td>
<td><strong>X</strong></td>
<td><strong>X</strong></td>
<td><strong>10</strong></td>
<td><strong>000</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
<tr>
<td><strong>halt</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>X</strong></td>
<td><strong>0</strong></td>
<td><strong>X</strong></td>
<td><strong>X</strong></td>
<td><strong>00</strong></td>
<td><strong>000</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
<td><strong>0</strong></td>
</tr>
</tbody></table>
<p><code>完成控制信号与相对应指令之间的关系以后该表后，对于如何实现单周期依旧感到很模糊，不知道相对应的信号量具体的控制意义，因此尝试结合实验原理中的图2单周期CPU数据通路和控制线路图，思考三种类型的指令，R型、I型、J型指令的CPU处理过程。对于R型指令而言，主要是一些算术运算指令和逻辑运算，主要为取指令，解析指令，执行指令，将运算结果写回寄存器组，其不需要访问数据寄存器，下一条指令顺序下一条，即pc←pc+4，其中的一些运算则由控制单元得到指令的操作码以后，设置控制信号，控制各个模块执行不同操作或者数据选择器选择相对应的输入作为输出；对于I型指令，其包含指令种类比较多，存储器指令，需要对存储器进行读或写的操作，对于pc没有别的特别影响，而分支指令则下一个pc可能不是pc+4，需要依据其运算结果做相对应的跳转操作或者顺序执行操作；对于J型指令，其是跳转指令，跳转到指令中相对应的地址中，主要对pc进行操作。不同类型的指令，其进行的过程并非完成相同的，不同类型指令所使用的模块并不是一样的，所有的指令也不是都需要完整的五个处理阶段。结合CPU数据通路图以及指令相对应的控制信号后，对于每种指令的数据通路有了一个比较清晰的了解，对于每个控制信号与相对应的功能模块更加熟悉和了解，理清了如何设计单周期CPU，即将其模块化，并且在控制单元中依据指令的操作码，对各个模块的控制信号进行一定的设定，执行指令相对应的操作。</code></p>
<h5 id="CPU模块划分与实现"><a href="#CPU模块划分与实现" class="headerlink" title="CPU模块划分与实现"></a>CPU模块划分与实现</h5><p>依据图2 单周期CPU数据通路和控制线路图，将CPU划分为9个模块，没有完全依据单周期CPU数据通路图进行划分，主要依据数据通路图进行划分太冗余，因此将一些数据选择器合并进了部分功能模块中，实现简化。模块划分结果如图三所示。  </p>
<p><img src="https://cdn.jsdelivr.net/gh/PDPENG/jason-storage/blog-img/20220515095701.png"></p>
<h4 id="pcAdd"><a href="#pcAdd" class="headerlink" title="pcAdd"></a>pcAdd</h4><ul>
<li><p>模块功能：根据控制信号PCSrc，计算获得下一个pc以及控制信号Reset重置。</p>
</li>
<li><p>实现思路：首先先决定何时引起触发，决定敏感变量，该模块选择将时钟的下降沿以及控制信号Reset的下降沿作为敏感变量，主要是为了能够确保下一条pc能够正确得到。</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">module pcAdd(</span><br><span class="line">        input Reset,</span><br><span class="line">        input CLK,               //时钟</span><br><span class="line">        input [1:0] PCSrc,             //数据选择器输入</span><br><span class="line">        input [31:0] immediate,  //偏移量</span><br><span class="line">        input [25:0] addr,</span><br><span class="line">        input [31:0] curPC,</span><br><span class="line">        output reg[31:0] nextPC  //新指令地址</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        nextPC &lt;= 0;</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    reg [31:0] pc;</span><br><span class="line"></span><br><span class="line">    always@(negedge CLK or negedge Reset)</span><br><span class="line">    begin</span><br><span class="line">        <span class="keyword">if</span>(!Reset) begin</span><br><span class="line">            nextPC &lt;= 0;</span><br><span class="line">        end</span><br><span class="line">        <span class="keyword">else</span> begin</span><br><span class="line">            pc &lt;= curPC + 4;</span><br><span class="line">            <span class="keyword">case</span>(PCSrc)</span><br><span class="line">                2<span class="string">&#x27;b00: nextPC &lt;= curPC + 4;</span></span><br><span class="line"><span class="string">                2&#x27;</span>b01: nextPC &lt;= curPC + 4 + immediate * 4;</span><br><span class="line">                2<span class="string">&#x27;b10: nextPC &lt;= &#123;pc[31:28],addr,2&#x27;</span>b00&#125;;</span><br><span class="line">                2<span class="string">&#x27;b11: nextPC &lt;= nextPC;</span></span><br><span class="line"><span class="string">            endcase</span></span><br><span class="line"><span class="string">        end</span></span><br><span class="line"><span class="string">    end</span></span><br><span class="line"><span class="string">endmodule</span></span><br></pre></td></tr></table></figure>

<h4 id="PC"><a href="#PC" class="headerlink" title="PC"></a>PC</h4><ul>
<li><p>模块功能：根据控制信号PCWre，判断pc是否改变以及根据Reset信号判断是否重置</p>
</li>
<li><p>实现思路：将时钟信号的上升沿和控制信号Reset作为敏感变量，使得pc在上升沿的时候发生改变或被重置。</p>
</li>
<li><p>主要实现代码：</p>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">module PC(</span><br><span class="line">       input CLK,               //时钟</span><br><span class="line">       input Reset,             //是否重置地址。0-初始化PC，否则接受新地址</span><br><span class="line">       input PCWre,             //是否接受新的地址。0-不更改；1-可以更改</span><br><span class="line">       input [1:0] PCSrc,             //数据选择器输入</span><br><span class="line">       input [31:0] nextPC,  //新指令地址</span><br><span class="line">       output reg[31:0] curPC //当前指令的地址</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        curPC &lt;= 0;</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    always@(posedge CLK or negedge Reset)</span><br><span class="line">    begin</span><br><span class="line">        <span class="keyword">if</span>(!Reset) // Reset == 0, PC = 0</span><br><span class="line">            begin</span><br><span class="line">                curPC &lt;= 0;</span><br><span class="line">            end</span><br><span class="line">        <span class="keyword">else</span> </span><br><span class="line">            begin</span><br><span class="line">                <span class="keyword">if</span>(PCWre) // PCWre == 1</span><br><span class="line">                    begin </span><br><span class="line">                        curPC &lt;= nextPC;</span><br><span class="line">                    end</span><br><span class="line">                <span class="keyword">else</span>    // PCWre == 0, halt</span><br><span class="line">                    begin</span><br><span class="line">                        curPC &lt;= curPC;</span><br><span class="line">                    end</span><br><span class="line">            end</span><br><span class="line">    end</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h4 id="InsMEM"><a href="#InsMEM" class="headerlink" title="InsMEM"></a>InsMEM</h4><ul>
<li><p>模块功能：依据当前pc，读取指令寄存器中，相对应地址的指令</p>
</li>
<li><p>实现思路：将pc的输入作为敏感变量，当pc发生改变的时候，则进行指令的读取，根据相关的地址，输出指令寄存器中相对应的指令</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">//ROM</span><br><span class="line">//instruction memory 指令寄存器</span><br><span class="line">module InsMEM(</span><br><span class="line">        input [31:0] IAddr,</span><br><span class="line">        input InsMemRW,             //状态为<span class="string">&#x27;0&#x27;</span>，写指令寄存器，否则为读指令寄存器</span><br><span class="line">        output reg[31:0] IDataOut</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    reg [7:0] rom[128:0];  // 存储器定义必须用reg类型，存储器存储单元8位长度，共128个存储单元，可以存32条指令</span><br><span class="line"></span><br><span class="line">    // 加载数据到存储器rom。注意：必须使用绝对路径</span><br><span class="line">    initial </span><br><span class="line">    begin</span><br><span class="line">        <span class="variable">$readmemb</span>(<span class="string">&quot;地址\\rom.txt&quot;</span>, rom);</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    //大端模式</span><br><span class="line">    always@(IAddr or InsMemRW)</span><br><span class="line">    begin</span><br><span class="line">        //取指令</span><br><span class="line">        <span class="keyword">if</span>(InsMemRW)</span><br><span class="line">            begin</span><br><span class="line">                IDataOut[7:0] = rom[IAddr + 3];</span><br><span class="line">                IDataOut[15:8] = rom[IAddr + 2];</span><br><span class="line">                IDataOut[23:16] = rom[IAddr + 1];</span><br><span class="line">                IDataOut[31:24] = rom[IAddr];</span><br><span class="line">            end </span><br><span class="line">            //<span class="variable">$display</span>(<span class="string">&quot;iaddr: %d insmemrw: %d inst; %d&quot;</span>,IAddr, InsMemRW, IDataOut);</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h4 id="InstructionCut"><a href="#InstructionCut" class="headerlink" title="InstructionCut"></a>InstructionCut</h4><ul>
<li><p>模块功能：对指令进行分割，获得相对应的指令信息</p>
</li>
<li><p>实现思路：根据各种类型的指令结构，将指令分割，得到相对应的信息</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">//指令分割</span><br><span class="line">module InstructionCut(</span><br><span class="line">        input [31:0] instruction,</span><br><span class="line">        output reg[5:0] op,</span><br><span class="line">        output reg[4:0] rs,</span><br><span class="line">        output reg[4:0] rt,</span><br><span class="line">        output reg[4:0] rd,</span><br><span class="line">        output reg[4:0] sa,</span><br><span class="line">        output reg[15:0] immediate,</span><br><span class="line">        output reg[25:0] addr</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        op = 5<span class="string">&#x27;b00000;</span></span><br><span class="line"><span class="string">        rs = 5&#x27;</span>b00000;</span><br><span class="line">        rt = 5<span class="string">&#x27;b00000;</span></span><br><span class="line"><span class="string">        rd = 5&#x27;</span>b00000;</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    always@(instruction) </span><br><span class="line">    begin</span><br><span class="line">        op = instruction[31:26];</span><br><span class="line">        rs = instruction[25:21];</span><br><span class="line">        rt = instruction[20:16];</span><br><span class="line">        rd = instruction[15:11];</span><br><span class="line">        sa = instruction[10:6];</span><br><span class="line">        immediate = instruction[15:0];</span><br><span class="line">        addr = instruction[25:0];</span><br><span class="line">    end</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h4 id="ControlUnit"><a href="#ControlUnit" class="headerlink" title="ControlUnit"></a>ControlUnit</h4><ul>
<li><p>模块功能：控制单元，依据指令的操作码(op)以及标记符(ZERO)，输出PCWre、ALUSrcB等控制信号，各控制信号的作用见实验原理的控制信号作用表（表3），从而达到控制各指令的目的.</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br><span class="line">89</span><br><span class="line">90</span><br><span class="line">91</span><br><span class="line">92</span><br><span class="line">93</span><br><span class="line">94</span><br><span class="line">95</span><br><span class="line">96</span><br><span class="line">97</span><br><span class="line">98</span><br><span class="line">99</span><br><span class="line">100</span><br><span class="line">101</span><br><span class="line">102</span><br><span class="line">103</span><br><span class="line">104</span><br><span class="line">105</span><br><span class="line">106</span><br><span class="line">107</span><br><span class="line">108</span><br><span class="line">109</span><br><span class="line">110</span><br><span class="line">111</span><br><span class="line">112</span><br><span class="line">113</span><br><span class="line">114</span><br><span class="line">115</span><br><span class="line">116</span><br><span class="line">117</span><br><span class="line">118</span><br><span class="line">119</span><br><span class="line">120</span><br><span class="line">121</span><br><span class="line">122</span><br><span class="line">123</span><br><span class="line">124</span><br><span class="line">125</span><br><span class="line">126</span><br><span class="line">127</span><br><span class="line">128</span><br><span class="line">129</span><br><span class="line">130</span><br><span class="line">131</span><br><span class="line">132</span><br><span class="line">133</span><br><span class="line">134</span><br><span class="line">135</span><br><span class="line">136</span><br><span class="line">137</span><br><span class="line">138</span><br><span class="line">139</span><br><span class="line">140</span><br><span class="line">141</span><br><span class="line">142</span><br><span class="line">143</span><br><span class="line">144</span><br><span class="line">145</span><br><span class="line">146</span><br><span class="line">147</span><br><span class="line">148</span><br><span class="line">149</span><br><span class="line">150</span><br><span class="line">151</span><br><span class="line">152</span><br><span class="line">153</span><br><span class="line">154</span><br><span class="line">155</span><br><span class="line">156</span><br><span class="line">157</span><br><span class="line">158</span><br><span class="line">159</span><br><span class="line">160</span><br><span class="line">161</span><br><span class="line">162</span><br><span class="line">163</span><br><span class="line">164</span><br><span class="line">165</span><br><span class="line">166</span><br><span class="line">167</span><br><span class="line">168</span><br><span class="line">169</span><br><span class="line">170</span><br><span class="line">171</span><br><span class="line">172</span><br><span class="line">173</span><br><span class="line">174</span><br><span class="line">175</span><br><span class="line">176</span><br><span class="line">177</span><br><span class="line">178</span><br><span class="line">179</span><br><span class="line">180</span><br><span class="line">181</span><br><span class="line">182</span><br><span class="line">183</span><br><span class="line">184</span><br><span class="line">185</span><br><span class="line">186</span><br><span class="line">187</span><br><span class="line">188</span><br><span class="line">189</span><br><span class="line">190</span><br><span class="line">191</span><br><span class="line">192</span><br><span class="line">193</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">//Control Unit</span><br><span class="line">module ControlUnit(</span><br><span class="line">        input zero,         //ALU运算结果是否为0，为0时候为1</span><br><span class="line">        input [5:0] op,     //指令的操作码</span><br><span class="line">        output reg PCWre,       //PC是否更改的信号量，为0时候不更改，否则可以更改</span><br><span class="line">        output reg ExtSel,      //立即数扩展的信号量，为0时候为0扩展，否则为符号扩展</span><br><span class="line">        output reg InsMemRW,    //指令寄存器的状态操作符，为0的时候写指令寄存器，否则为读指令寄存器</span><br><span class="line">        output reg RegDst,      //写寄存器组寄存器的地址，为0的时候地址来自rt，为1的时候地址来自rd</span><br><span class="line">        output reg RegWre,      //寄存器组写使能，为1的时候可写</span><br><span class="line">        output reg ALUSrcA,     //控制ALU数据A的选择端的输入，为0的时候，来自寄存器堆data1输出，为1的时候来自移位数sa</span><br><span class="line">        output reg ALUSrcB,     //控制ALU数据B的选择端的输入，为0的时候，来自寄存器堆data2输出，为1时候来自扩展过的立即数</span><br><span class="line">        output reg [1:0]PCSrc,  //获取下一个pc的地址的数据选择器的选择端输入</span><br><span class="line">        output reg [2:0]ALUOp,  //ALU 8种运算功能选择(000-111)</span><br><span class="line">        output reg mRD,         //数据存储器读控制信号，为0读</span><br><span class="line">        output reg mWR,         //数据存储器写控制信号，为0写</span><br><span class="line">        output reg DBDataSrc    //数据保存的选择端，为0来自ALU运算结果的输出，为1来自数据寄存器（Data MEM）的输出        </span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        InsMemRW = 1;</span><br><span class="line">        PCWre = 1;</span><br><span class="line">        mRD = 0;</span><br><span class="line">        mWR = 0;</span><br><span class="line">        DBDataSrc = 0;</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    always@(op or zero) </span><br><span class="line">    begin</span><br><span class="line">        PCWre = (op == 6<span class="string">&#x27;b111111) ? 0 : 1;   //halt</span></span><br><span class="line"><span class="string">        InsMemRW = (op == 6&#x27;</span>b111111) ? 0 : 1;    </span><br><span class="line">        mWR = (op == 6<span class="string">&#x27;b100110) ? 1 : 0;     //sw</span></span><br><span class="line"><span class="string">        mRD = (op == 6&#x27;</span>b100111) ? 1 : 0;     //lw</span><br><span class="line">        DBDataSrc = (op == 6<span class="string">&#x27;b100111) ? 1 : 0;</span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">        case(op)</span></span><br><span class="line"><span class="string">            //addi</span></span><br><span class="line"><span class="string">            6&#x27;</span>b000001:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 1;</span><br><span class="line">                    RegDst = 0;</span><br><span class="line">                    RegWre = 1;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 1;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b00;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b000;</span><br><span class="line">                end</span><br><span class="line">            //ori</span><br><span class="line">            6<span class="string">&#x27;b010000:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 1;</span></span><br><span class="line"><span class="string">                    RegDst = 0;</span></span><br><span class="line"><span class="string">                    RegWre = 1;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 1;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b011;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //add</span></span><br><span class="line"><span class="string">            6&#x27;</span>b000000:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 0;</span><br><span class="line">                    RegDst = 1;</span><br><span class="line">                    RegWre = 1;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 0;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b00;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b000;</span><br><span class="line">                end</span><br><span class="line">            //sub</span><br><span class="line">            6<span class="string">&#x27;b000010:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 1;</span></span><br><span class="line"><span class="string">                    RegDst = 1;</span></span><br><span class="line"><span class="string">                    RegWre = 1;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 0;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b001;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //and</span></span><br><span class="line"><span class="string">            6&#x27;</span>b010001:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 0;</span><br><span class="line">                    RegDst = 1;</span><br><span class="line">                    RegWre = 1;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 0;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b00;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b100;</span><br><span class="line">                end</span><br><span class="line">            //or</span><br><span class="line">            6<span class="string">&#x27;b010010:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 0;</span></span><br><span class="line"><span class="string">                    RegDst = 1;</span></span><br><span class="line"><span class="string">                    RegWre = 1;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 0;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b011;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //sll</span></span><br><span class="line"><span class="string">            6&#x27;</span>b011000:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 0;</span><br><span class="line">                    RegDst = 1;</span><br><span class="line">                    RegWre = 1;</span><br><span class="line">                    ALUSrcA = 1;</span><br><span class="line">                    ALUSrcB = 0;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b00;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b010;</span><br><span class="line">                end</span><br><span class="line">            //bne</span><br><span class="line">            6<span class="string">&#x27;b110001:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 1;</span></span><br><span class="line"><span class="string">                    RegDst = 0;</span></span><br><span class="line"><span class="string">                    RegWre = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 0;</span></span><br><span class="line"><span class="string">                    PCSrc = zero ? 2&#x27;</span>b00 : 2<span class="string">&#x27;b01;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b001;</span><br><span class="line">                end</span><br><span class="line">            //slti</span><br><span class="line">            6<span class="string">&#x27;b011011:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 1;</span></span><br><span class="line"><span class="string">                    RegDst = 0;</span></span><br><span class="line"><span class="string">                    RegWre = 1;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 1;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b101;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //beq</span></span><br><span class="line"><span class="string">            6&#x27;</span>b110000:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 1;</span><br><span class="line">                    RegDst = 0;</span><br><span class="line">                    RegWre = 0;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 0;</span><br><span class="line">                    PCSrc = zero ? 2<span class="string">&#x27;b01 : 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b001;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //sw</span></span><br><span class="line"><span class="string">            6&#x27;</span>b100110:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 1;</span><br><span class="line">                    RegDst = 0;</span><br><span class="line">                    RegWre = 0;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 1;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b00;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b000;</span><br><span class="line">                end</span><br><span class="line">            //lw</span><br><span class="line">            6<span class="string">&#x27;b100111:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 1;</span></span><br><span class="line"><span class="string">                    RegDst = 0;</span></span><br><span class="line"><span class="string">                    RegWre = 1;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 1;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b00;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b000;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">            //j</span></span><br><span class="line"><span class="string">            6&#x27;</span>b111000:</span><br><span class="line">                begin</span><br><span class="line">                    ExtSel = 0;</span><br><span class="line">                    RegDst = 0;</span><br><span class="line">                    RegWre = 0;</span><br><span class="line">                    ALUSrcA = 0;</span><br><span class="line">                    ALUSrcB = 0;</span><br><span class="line">                    PCSrc = 2<span class="string">&#x27;b10;</span></span><br><span class="line"><span class="string">                    ALUOp = 3&#x27;</span>b000;</span><br><span class="line">                end</span><br><span class="line">            //halt</span><br><span class="line">            6<span class="string">&#x27;b111111:</span></span><br><span class="line"><span class="string">                begin</span></span><br><span class="line"><span class="string">                    ExtSel = 0;</span></span><br><span class="line"><span class="string">                    RegDst = 0;</span></span><br><span class="line"><span class="string">                    RegWre = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcA = 0;</span></span><br><span class="line"><span class="string">                    ALUSrcB = 0;</span></span><br><span class="line"><span class="string">                    PCSrc = 2&#x27;</span>b11;</span><br><span class="line">                    ALUOp = 3<span class="string">&#x27;b000;</span></span><br><span class="line"><span class="string">                end</span></span><br><span class="line"><span class="string">        endcase</span></span><br><span class="line"><span class="string">    end</span></span><br><span class="line"><span class="string">endmodule</span></span><br></pre></td></tr></table></figure>

<h4 id="RegisterFile"><a href="#RegisterFile" class="headerlink" title="RegisterFile"></a>RegisterFile</h4><ul>
<li><p>模块功能：寄存器组，通过控制单元输出的控制信号，进行相对应的读或写操作</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">//寄存器组</span><br><span class="line">module RegisterFile(</span><br><span class="line">        input CLK,                  //时钟</span><br><span class="line">        input [4:0] ReadReg1,    //rs寄存器地址输入端口</span><br><span class="line">        input [4:0] ReadReg2,    //rt寄存器地址输入端口</span><br><span class="line">        input [31:0] WriteData,     //写入寄存器的数据输入端口</span><br><span class="line">        input [4:0] WriteReg,       //将数据写入的寄存器端口，其地址来源rt或rd字段</span><br><span class="line">        input RegWre,               //WE，写使能信号，为1时，在时钟边沿触发写入</span><br><span class="line">        output reg[31:0] ReadData1,  //rs寄存器数据输出端口</span><br><span class="line">        output reg[31:0] ReadData2   //rt寄存器数据输出端口</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        ReadData1 &lt;= 0;</span><br><span class="line">        ReadData2 &lt;= 0;</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">    reg [31:0] regFile[0:31]; //  寄存器定义必须用reg类型</span><br><span class="line">    <span class="built_in">integer</span> i;</span><br><span class="line">    initial begin</span><br><span class="line">        <span class="keyword">for</span> (i = 0; i &lt; 32; i = i+ 1) regFile[i] &lt;= 0;  </span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    always@(ReadReg1 or ReadReg2) </span><br><span class="line">    begin</span><br><span class="line">        ReadData1 = regFile[ReadReg1];</span><br><span class="line">        ReadData2 = regFile[ReadReg2];</span><br><span class="line">        //<span class="variable">$display</span>(<span class="string">&quot;regfile %d %d\n&quot;</span>, ReadReg1, ReadReg2);</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    always@(negedge CLK)</span><br><span class="line">    begin</span><br><span class="line">        //<span class="variable">$0</span>恒为0，所以写入寄存器的地址不能为0</span><br><span class="line">        <span class="keyword">if</span>(RegWre &amp;&amp; WriteReg)</span><br><span class="line">            begin</span><br><span class="line">                regFile[WriteReg] &lt;= WriteData;</span><br><span class="line">            end</span><br><span class="line">    end</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h4 id="ALU"><a href="#ALU" class="headerlink" title="ALU"></a>ALU</h4><ul>
<li><p>模块功能：算术逻辑单元，对两个输入依据ALUOp进行相对应的运算</p>
</li>
<li><p>实现思路：依据实验原理中的ALU运算功能表(表2)完成操作码对应的操作</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">module ALU(</span><br><span class="line">        input ALUSrcA,</span><br><span class="line">        input ALUSrcB,</span><br><span class="line">        input [31:0] ReadData1,</span><br><span class="line">        input [31:0] ReadData2,</span><br><span class="line">        input [4:0] sa,</span><br><span class="line">        input [31:0] extend,</span><br><span class="line">        input [2:0] ALUOp,</span><br><span class="line">        output reg zero,</span><br><span class="line">        output reg[31:0] result</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    reg [31:0] A;</span><br><span class="line">    reg [31:0] B;</span><br><span class="line"></span><br><span class="line">    always@(ReadData1 or ReadData2 or ALUSrcA or ALUSrcB or ALUOp) </span><br><span class="line">    begin</span><br><span class="line">        //定义两个输入端口</span><br><span class="line">        A = (ALUSrcA == 0) ? ReadData1 : sa;</span><br><span class="line">        B = (ALUSrcB == 0) ? ReadData2 : extend;</span><br><span class="line">        <span class="keyword">case</span>(ALUOp)</span><br><span class="line">            3<span class="string">&#x27;b000: result = A + B;</span></span><br><span class="line"><span class="string">            3&#x27;</span>b001: result = A - B;</span><br><span class="line">            3<span class="string">&#x27;b010: result = B &lt;&lt; A;</span></span><br><span class="line"><span class="string">            3&#x27;</span>b011: result = A | B;</span><br><span class="line">            3<span class="string">&#x27;b100: result = A &amp; B;</span></span><br><span class="line"><span class="string">            3&#x27;</span>b101: result = (A &lt; B) ? 1 : 0;</span><br><span class="line">            3<span class="string">&#x27;b110: result = (((ReadData1 &lt; ReadData2) &amp;&amp; (ReadData1[31] == ReadData2[31] )) ||( ( ReadData1[31] ==1 &amp;&amp; ReadData2[31] == 0))) ? 1:0;</span></span><br><span class="line"><span class="string">            3&#x27;</span>b111: result = A ^ B;</span><br><span class="line">        endcase</span><br><span class="line">        zero = (result == 0) ? 1 : 0;</span><br><span class="line">    end </span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h4 id="DataMEM"><a href="#DataMEM" class="headerlink" title="DataMEM"></a>DataMEM</h4><ul>
<li><p>模块功能：数据存储器，通过控制信号，对数据寄存器进行读或者写操作，并且此处模块额外合并了输出DB的数据选择器，此模块同时输出写回寄存器组的数据DB。</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">//RAM</span><br><span class="line">//data memory 数据存储器</span><br><span class="line">module DataMEM(</span><br><span class="line">        /*</span><br><span class="line">            Daddr，数据存储器地址输入端口</span><br><span class="line">            DataIn，数据存储器数据输入端口</span><br><span class="line">            DataOut，数据存储器数据输出端口</span><br><span class="line">            mRD，数据存储器读控制信号，为0读</span><br><span class="line">            mWR，数据存储器写控制信号，为0写</span><br><span class="line">        */</span><br><span class="line">        input mRD,</span><br><span class="line">        input mWR,</span><br><span class="line">        input CLK,</span><br><span class="line">        input DBDataSrc,</span><br><span class="line">        input [31:0] DAddr,</span><br><span class="line">        input [31:0] DataIn,</span><br><span class="line">        output reg[31:0] DataOut,</span><br><span class="line">        output reg[31:0] DB</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin </span><br><span class="line">        DB &lt;= 16<span class="string">&#x27;b0;</span></span><br><span class="line"><span class="string">    end</span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">     reg [7:0] ram [0:31];     // 存储器定义必须用reg类型    </span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">    always@(mRD or DAddr or DBDataSrc)</span></span><br><span class="line"><span class="string">    begin</span></span><br><span class="line"><span class="string">        //读</span></span><br><span class="line"><span class="string">        DataOut[7:0] = mRD ? ram[DAddr + 3] : 8&#x27;</span>bz; // z 为高阻态     </span><br><span class="line">        DataOut[15:8] = mRD ? ram[DAddr + 2] : 8<span class="string">&#x27;bz;     </span></span><br><span class="line"><span class="string">        DataOut[23:16] = mRD ? ram[DAddr + 1] : 8&#x27;</span>bz;     </span><br><span class="line">        DataOut[31:24] = mRD ? ram[DAddr] : 8<span class="string">&#x27;bz;</span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">        DB = (DBDataSrc == 0) ? DAddr : DataOut;</span></span><br><span class="line"><span class="string">    end</span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">    always@(negedge CLK)</span></span><br><span class="line"><span class="string">    begin   </span></span><br><span class="line"><span class="string">        //写</span></span><br><span class="line"><span class="string">        if(mWR)</span></span><br><span class="line"><span class="string">            begin</span></span><br><span class="line"><span class="string">                ram[DAddr] = DataIn[31:24];    </span></span><br><span class="line"><span class="string">                ram[DAddr + 1] = DataIn[23:16];</span></span><br><span class="line"><span class="string">                ram[DAddr + 2] = DataIn[15:8];     </span></span><br><span class="line"><span class="string">                ram[DAddr + 3] = DataIn[7:0];    </span></span><br><span class="line"><span class="string">            end</span></span><br><span class="line"><span class="string">        //$display(&quot;mwr: %d $12 %d %d %d %d&quot;, mWR, ram[12], ram[13], ram[14], ram[15]);</span></span><br><span class="line"><span class="string">    end</span></span><br><span class="line"><span class="string"></span></span><br><span class="line"><span class="string">endmodule</span></span><br></pre></td></tr></table></figure>

<h4 id="SignZeroExtend"><a href="#SignZeroExtend" class="headerlink" title="SignZeroExtend"></a>SignZeroExtend</h4><ul>
<li><p>模块功能：根据指令相关的控制信号ExtSel，对立即数进行扩展。</p>
</li>
<li><p>实现思路：根据控制信号ExtSel判断是0扩展还是符号扩展，然后进行相对应的扩展</p>
<ul>
<li>主要实现代码：</li>
</ul>
</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line">module SignZeroExtend(</span><br><span class="line">        input wire [15:0] immediate,    //立即数</span><br><span class="line">        input ExtSel,                   //状态<span class="string">&#x27;0&#x27;</span>,0扩展，否则符号位扩展</span><br><span class="line">        output [31:0] extendImmediate</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    always@(extendImmediate)</span><br><span class="line">    begin</span><br><span class="line">        <span class="variable">$display</span>(<span class="string">&quot;%d&quot;</span>, extendImmediate[31]);</span><br><span class="line">    end</span><br><span class="line"></span><br><span class="line">    assign extendImmediate[15:0] = immediate;</span><br><span class="line">    assign extendImmediate[31:16] = ExtSel ? (immediate[15] ? 16<span class="string">&#x27;hffff : 16&#x27;</span>h0000) : 16<span class="string">&#x27;h0000;</span></span><br><span class="line"><span class="string">endmodule</span></span><br></pre></td></tr></table></figure>

<h4 id="顶层模块：SingleCycleCPU"><a href="#顶层模块：SingleCycleCPU" class="headerlink" title="顶层模块：SingleCycleCPU"></a>顶层模块：SingleCycleCPU</h4><ul>
<li>实现思路：在顶层模块中将各个已实现的底层模块进行实列，并且用verilog语言将各个模块用线连接起来</li>
<li>代码</li>
</ul>
<figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br><span class="line">89</span><br><span class="line">90</span><br><span class="line">91</span><br><span class="line">92</span><br><span class="line">93</span><br><span class="line">94</span><br><span class="line">95</span><br><span class="line">96</span><br><span class="line">97</span><br><span class="line">98</span><br><span class="line">99</span><br><span class="line">100</span><br><span class="line">101</span><br><span class="line">102</span><br><span class="line">103</span><br><span class="line">104</span><br><span class="line">105</span><br><span class="line">106</span><br><span class="line">107</span><br><span class="line">108</span><br><span class="line">109</span><br><span class="line">110</span><br><span class="line">111</span><br><span class="line">112</span><br><span class="line">113</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line"></span><br><span class="line">module SingleCycleCPU(</span><br><span class="line">        input CLK,</span><br><span class="line">        input Reset,</span><br><span class="line">        output [31:0] curPC,</span><br><span class="line">        output [31:0] nextPC,</span><br><span class="line">        output [31:0] instruction,</span><br><span class="line">        output [5:0] op,</span><br><span class="line">        output [4:0] rs,</span><br><span class="line">        output [4:0] rt,</span><br><span class="line">        output [4:0] rd,</span><br><span class="line">        output [31:0] DB,</span><br><span class="line">        output [31:0] A,</span><br><span class="line">        output [31:0] B,</span><br><span class="line">        output [31:0] result,</span><br><span class="line">        output [1:0] PCSrc,</span><br><span class="line">        output zero,</span><br><span class="line">        output PCWre,       //PC是否更改的信号量，为0时候不更改，否则可以更改</span><br><span class="line">        output ExtSel,      //立即数扩展的信号量，为0时候为0扩展，否则为符号扩展</span><br><span class="line">        output InsMemRW,    //指令寄存器的状态操作符，为0的时候写指令寄存器，否则为读指令寄存器</span><br><span class="line">        output RegDst,      //写寄存器组寄存器的地址，为0的时候地址来自rt，为1的时候地址来自rd</span><br><span class="line">        output RegWre,      //寄存器组写使能，为1的时候可写</span><br><span class="line">        output ALUSrcA,     //控制ALU数据A的选择端的输入，为0的时候，来自寄存器堆data1输出，为1的时候来自移位数sa</span><br><span class="line">        output ALUSrcB,     //控制ALU数据B的选择端的输入，为0的时候，来自寄存器堆data2输出，为1时候来自扩展过的立即数</span><br><span class="line">        output [2:0]ALUOp,  //ALU 8种运算功能选择(000-111)</span><br><span class="line">        output mRD,         //数据存储器读控制信号，为0读</span><br><span class="line">        output mWR,         //数据存储器写控制信号，为0写</span><br><span class="line">        output DBDataSrc    //数据保存的选择端，为0来自ALU运算结果的输出，为1来自数据寄存器（Data MEM）的输出  </span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    wire [31:0] extend;</span><br><span class="line">    wire [31:0] DataOut;</span><br><span class="line">    wire[4:0] sa;</span><br><span class="line">    wire[15:0] immediate;</span><br><span class="line">    wire[25:0] addr;</span><br><span class="line"></span><br><span class="line">    pcAdd pcAdd(.Reset(Reset),</span><br><span class="line">                .CLK(CLK),</span><br><span class="line">                .PCSrc(PCSrc),</span><br><span class="line">                .immediate(extend),</span><br><span class="line">                .addr(addr),</span><br><span class="line">                .curPC(curPC),</span><br><span class="line">                .nextPC(nextPC));</span><br><span class="line"></span><br><span class="line">    PC pc(.CLK(CLK),</span><br><span class="line">          .Reset(Reset),</span><br><span class="line">          .PCWre(PCWre),</span><br><span class="line">          .PCSrc(PCSrc),</span><br><span class="line">          .nextPC(nextPC),</span><br><span class="line">          .curPC(curPC));</span><br><span class="line"></span><br><span class="line">    InsMEM InsMEM(.IAddr(curPC), </span><br><span class="line">                .InsMemRW(InsMemRW), </span><br><span class="line">                .IDataOut(instruction));</span><br><span class="line"></span><br><span class="line">    InstructionCut InstructionCut(.instruction(instruction),</span><br><span class="line">                                  .op(op),</span><br><span class="line">                                  .rs(rs),</span><br><span class="line">                                  .rt(rt),</span><br><span class="line">                                  .rd(rd),</span><br><span class="line">                                  .sa(sa),</span><br><span class="line">                                  .immediate(immediate),</span><br><span class="line">                                  .addr(addr));</span><br><span class="line"></span><br><span class="line">    ControlUnit ControlUnit(.zero(zero),</span><br><span class="line">                            .op(op),</span><br><span class="line">                            .PCWre(PCWre),</span><br><span class="line">                            .ExtSel(ExtSel),</span><br><span class="line">                            .InsMemRW(InsMemRW),</span><br><span class="line">                            .RegDst(RegDst),</span><br><span class="line">                            .RegWre(RegWre),</span><br><span class="line">                            .ALUSrcA(ALUSrcA),</span><br><span class="line">                            .ALUSrcB(ALUSrcB),</span><br><span class="line">                            .PCSrc(PCSrc),</span><br><span class="line">                            .ALUOp(ALUOp),</span><br><span class="line">                            .mRD(mRD),</span><br><span class="line">                            .mWR(mWR),</span><br><span class="line">                            .DBDataSrc(DBDataSrc));</span><br><span class="line"></span><br><span class="line">    RegisterFile RegisterFile(.CLK(CLK),</span><br><span class="line">                              .ReadReg1(rs),</span><br><span class="line">                              .ReadReg2(rt),</span><br><span class="line">                              .WriteData(DB),</span><br><span class="line">                              .WriteReg(RegDst ? rd : rt),</span><br><span class="line">                              .RegWre(RegWre),</span><br><span class="line">                              .ReadData1(A),</span><br><span class="line">                              .ReadData2(B));</span><br><span class="line"></span><br><span class="line">    ALU alu(.ALUSrcA(ALUSrcA),</span><br><span class="line">            .ALUSrcB(ALUSrcB),</span><br><span class="line">            .ReadData1(A),</span><br><span class="line">            .ReadData2(B),</span><br><span class="line">            .sa(sa),</span><br><span class="line">            .extend(extend),</span><br><span class="line">            .ALUOp(ALUOp),</span><br><span class="line">            .zero(zero),</span><br><span class="line">            .result(result));</span><br><span class="line"></span><br><span class="line">    DataMEM DataMEM(.mRD(mRD),</span><br><span class="line">                    .mWR(mWR),</span><br><span class="line">                    .CLK(CLK),</span><br><span class="line">                    .DBDataSrc(DBDataSrc),</span><br><span class="line">                    .DAddr(result),</span><br><span class="line">                    .DataIn(B),</span><br><span class="line">                    .DataOut(DataOut),</span><br><span class="line">                    .DB(DB));</span><br><span class="line"></span><br><span class="line">    SignZeroExtend SignZeroExtend(.immediate(immediate),</span><br><span class="line">                                  .ExtSel(ExtSel),</span><br><span class="line">                                  .extendImmediate(extend));</span><br><span class="line"></span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h3 id="CPU正确性的验证"><a href="#CPU正确性的验证" class="headerlink" title="CPU正确性的验证"></a>CPU正确性的验证</h3><h4 id="仿真程序："><a href="#仿真程序：" class="headerlink" title="仿真程序："></a>仿真程序：</h4><figure class="highlight bash"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br></pre></td><td class="code"><pre><span class="line">`timescale 1ns / 1ps</span><br><span class="line"></span><br><span class="line">module TestSingleCycleCpu();</span><br><span class="line">    // Inputs</span><br><span class="line">    reg CLK;</span><br><span class="line">    reg Reset;</span><br><span class="line"></span><br><span class="line">    // Outputs</span><br><span class="line">    wire [1:0] PCSrc;</span><br><span class="line">    wire [5:0] op;</span><br><span class="line">    wire [4:0] rs;</span><br><span class="line">    wire [4:0] rt;</span><br><span class="line">    wire [4:0] rd;</span><br><span class="line">    wire [31:0] DB;</span><br><span class="line">    wire [31:0] result;</span><br><span class="line">    wire [31:0] curPC;</span><br><span class="line">    wire [31:0] nextPC;</span><br><span class="line">    wire [31:0] instruction;</span><br><span class="line">    wire [31:0] A;</span><br><span class="line">    wire [31:0] B;</span><br><span class="line">    wire zero;</span><br><span class="line">    wire PCWre;       //PC是否更改的信号量，为0时候不更改，否则可以更改</span><br><span class="line">    wire ExtSel;      //立即数扩展的信号量，为0时候为0扩展，否则为符号扩展</span><br><span class="line">    wire InsMemRW;    //指令寄存器的状态操作符，为0的时候写指令寄存器，否则为读指令寄存器</span><br><span class="line">    wire RegDst;      //写寄存器组寄存器的地址，为0的时候地址来自rt，为1的时候地址来自rd</span><br><span class="line">    wire RegWre;      //寄存器组写使能，为1的时候可写</span><br><span class="line">    wire ALUSrcA;     //控制ALU数据A的选择端的输入，为0的时候，来自寄存器堆data1输出，为1的时候来自移位数sa</span><br><span class="line">    wire ALUSrcB;     //控制ALU数据B的选择端的输入，为0的时候，来自寄存器堆data2输出，为1时候来自扩展过的立即数</span><br><span class="line">    wire [2:0]ALUOp;  //ALU 8种运算功能选择(000-111)</span><br><span class="line">    wire mRD;         //数据存储器读控制信号，为0读</span><br><span class="line">    wire mWR;         //数据存储器写控制信号，为0写</span><br><span class="line">    wire DBDataSrc;    //数据保存的选择端，为0来自ALU运算结果的输出，为1来自数据寄存器（Data MEM）的输出  </span><br><span class="line">    // Instantiate the Unit Under Test (UUT)</span><br><span class="line">    SingleCycleCPU uut (</span><br><span class="line">        .CLK(CLK), </span><br><span class="line">        .Reset(Reset), </span><br><span class="line">        .curPC(curPC),</span><br><span class="line">        .nextPC(nextPC),</span><br><span class="line">        .instruction(instruction),</span><br><span class="line">        .op(op), </span><br><span class="line">        .rs(rs),</span><br><span class="line">        .rt(rt),</span><br><span class="line">        .rd(rd),</span><br><span class="line">        .DB(DB),</span><br><span class="line">        .A(A),</span><br><span class="line">        .B(B),</span><br><span class="line">        .result(result),</span><br><span class="line">        .PCSrc(PCSrc),</span><br><span class="line">        .zero(zero),</span><br><span class="line">        .PCWre(PCWre),</span><br><span class="line">        .ExtSel(ExtSel),</span><br><span class="line">        .InsMemRW(InsMemRW),</span><br><span class="line">        .RegDst(RegDst),</span><br><span class="line">        .RegWre(RegWre),</span><br><span class="line">        .ALUSrcA(ALUSrcA),</span><br><span class="line">        .ALUSrcB(ALUSrcB),</span><br><span class="line">        .ALUOp(ALUOp),</span><br><span class="line">        .mRD(mRD),</span><br><span class="line">        .mWR(mWR),</span><br><span class="line">        .DBDataSrc(DBDataSrc)</span><br><span class="line">    );</span><br><span class="line"></span><br><span class="line">    initial begin</span><br><span class="line">        // Initialize Inputs</span><br><span class="line">        CLK = 1;</span><br><span class="line">        Reset = 0;</span><br><span class="line"></span><br><span class="line">        CLK = !CLK;  // 下降沿，使PC先清零</span><br><span class="line">        Reset = 1;  // 清除保持信号</span><br><span class="line">        forever <span class="comment">#5</span></span><br><span class="line">        begin // 产生时钟信号，周期为50s</span><br><span class="line">             CLK = !CLK;</span><br><span class="line">        end</span><br><span class="line">    end</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<h5 id="程序代码测试"><a href="#程序代码测试" class="headerlink" title="程序代码测试"></a>程序代码测试</h5><table>
<thead>
<tr>
<th><strong>地址</strong></th>
<th><strong>汇编程序</strong></th>
<th><strong>指令代码</strong></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody><tr>
<td></td>
<td></td>
<td><strong>op（6）</strong></td>
<td><strong>rs(5)</strong></td>
<td><strong>rt(5)</strong></td>
<td><strong>rd(5)&#x2F;immediate (16)</strong></td>
</tr>
<tr>
<td><strong>0x00000000</strong></td>
<td>addi $1,$0,8</td>
<td><strong>000001</strong></td>
<td><strong>00000</strong></td>
<td><strong>00001</strong></td>
<td><strong>0000 0000 0000 1000</strong></td>
</tr>
<tr>
<td><strong>0x00000004</strong></td>
<td>ori $2,$0,2</td>
<td>010000</td>
<td><strong>00000</strong></td>
<td><strong>00010</strong></td>
<td><strong>0000 0000 0000 0010</strong></td>
</tr>
<tr>
<td><strong>0x00000008</strong></td>
<td>add $3,$2,$1</td>
<td>000000</td>
<td>00010</td>
<td>00001</td>
<td>0001 1000 0000 0000</td>
</tr>
<tr>
<td><strong>0x0000000C</strong></td>
<td>sub $5,$3,$2</td>
<td>000010</td>
<td>00011</td>
<td>00010</td>
<td>0010 1000 0000 0000</td>
</tr>
<tr>
<td><strong>0x00000010</strong></td>
<td>and $4,$5,$2</td>
<td>010001</td>
<td>00101</td>
<td>00010</td>
<td>0010 0000 0000 0000</td>
</tr>
<tr>
<td><strong>0x00000014</strong></td>
<td>or $8,$4,$2</td>
<td>010010</td>
<td>00100</td>
<td>00010</td>
<td>0100 0000 0000 0000</td>
</tr>
<tr>
<td><strong>0x00000018</strong></td>
<td>sll $8,$8,1</td>
<td>011000</td>
<td>00000</td>
<td>01000</td>
<td>0100 0000 0100 0000</td>
</tr>
<tr>
<td><strong>0x0000001C</strong></td>
<td>bne $8,$1,-2 (≠,转18)</td>
<td>110001</td>
<td>01000</td>
<td>00001</td>
<td>1111 1111 1111 1110</td>
</tr>
<tr>
<td><strong>0x00000020</strong></td>
<td>slti $6,$2,8</td>
<td>011011</td>
<td>00010</td>
<td>00110</td>
<td>0000 0000 0000 1000</td>
</tr>
<tr>
<td><strong>0x00000024</strong></td>
<td>slti $7,$6,0</td>
<td>011011</td>
<td>00110</td>
<td>00111</td>
<td>0000 0000 0000 0000</td>
</tr>
<tr>
<td><strong>0x00000028</strong></td>
<td>addi $7,$7,8</td>
<td>000001</td>
<td>00111</td>
<td>00111</td>
<td>0000 0000 0000 1000</td>
</tr>
<tr>
<td><strong>0x0000002C</strong></td>
<td>beq $7,$1,-2 (&#x3D;,转28)</td>
<td>110000</td>
<td>00111</td>
<td>00001</td>
<td>1111 1111 1111 1110</td>
</tr>
<tr>
<td><strong>0x00000030</strong></td>
<td>sw $2,4($1)</td>
<td>100110</td>
<td>00001</td>
<td>00010</td>
<td>0000 0000 0000 0100</td>
</tr>
<tr>
<td><strong>0x00000034</strong></td>
<td>lw $9,4($1)</td>
<td>100111</td>
<td>00001</td>
<td>01001</td>
<td>0000 0000 0000 0100</td>
</tr>
<tr>
<td><strong>0x00000038</strong></td>
<td><strong>j 0x00000040</strong></td>
<td>111000</td>
<td>00000</td>
<td>00000</td>
<td>0000 0000 0001 0000</td>
</tr>
<tr>
<td><strong>0x0000003C</strong></td>
<td>addi $10,$0,10</td>
<td><strong>000001</strong></td>
<td><strong>00000</strong></td>
<td><strong>01010</strong></td>
<td><strong>0000 0000 0000 1010</strong></td>
</tr>
<tr>
<td><strong>0x00000040</strong></td>
<td><strong>Halt</strong></td>
<td>111111</td>
<td>00000</td>
<td>00000</td>
<td>0000 0000 0000 0000</td>
</tr>
<tr>
<td><strong>0x00000044</strong></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td><strong>0x00000048</strong></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td><strong>0x0000004C</strong></td>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
</tbody></table>
<p><code>使用上面程序段进行测试CPU正确性，将其中的指令写入一个romData.txt文件中。   在模块InsMEM中进行读入（使用的路径为绝对路径）</code><br>(<span class="exturl" data-url="aHR0cHM6Ly9naXRodWIuY29tL0xpdS1ZVC9TaW5nbGVDeWNsZUNQVQ==">源码和实验报告<i class="fa fa-external-link-alt"></i></span>)</p>
<h4 id="总结"><a href="#总结" class="headerlink" title="总结"></a>总结</h4><p>本次实验中遇到的问题比较多。首先是关于CPU的设计，其次就是verilog语言。一开始不知道如何实现，感觉无从下手。主要通过分析实验原理中的图2 单周期CPU数据通路和控制线路图，分析各种指令的处理过程，学会将CPU内各个部分模块化，各个模块分别实现一定的功能，然后通过相对应的控制信号连接起来，这样就实现cpu设计。完成模块的划分以后，按照先前对每个模块功能预设进行完成，但是每个模块的敏感信号的选择还是很重要的，有些模块程序要在时钟信号上升沿触发，而有些模块要在时钟信号的下降沿触发，有些则将电平信号作为敏感信号，每个模块里面的敏感信号的选择都十分的重要，一开始没有太过注意导致出现了很多的问题，后面重新仔细的想指令的处理过程，重新规定了各个模块always@里面的敏感信号。<br>其次就是verilog里面的wire和reg两种变量类型，感觉这是比较大的坑。一开始不了解两者的区别，导致后面一堆报错。现在大致的清楚了二者的区别，wire主要起信号间连接的作用，例如顶层模块中，需要将各个模块连接起来，这时候只能用wire连接，不能使用reg，wire不保存状态，它的值的随时可以改变，不受时钟信号的影响，而reg则是寄存器的抽象表达，可以用于存储数值，例如指令寄存器和寄存器组以及数据寄存器里面的存储器必须为reg类型，用于保留数据。其次wire类型只能通过assign进行赋值，而reg类型只能在always里面被赋值，而涉及到always又有阻塞赋值和非阻塞赋值这个大坑，一开始也不知道怎么弄，就混用了，后面也是出现乱七八糟的问题，后面仔细学习了一下，敏感信号为电平信号的时候，采用阻塞赋值(&#x3D;),而敏感信号为时序信号的时候，采用非阻塞赋值(&lt;&#x3D;)。<br>再者就是烧板的时候的消抖问题。一开始没有进行消抖，然后总是按一下运行了几条指令，后面上网学习了一下如何消抖，顺利的解决了该问题。<br>还有比较疑惑的问题就是使用vivado进行Implemention的时候，有时候进行Running place_design这一部分的时候就一直在此处运行，没有任何进度了，网上也没有合理的解释，然后新新建个项目，将里面的代码复制进去又可以正常的运行了，这个问题目前尚未解决。<br>本次单周期CPU设计实验，将计组理论课上所讲的指令处理过程自己重复并实现了单周期CPU的设计，加深了CPU处理指令过程理解，之前由于计组理论学的不是特别清楚，本次实验加深了印象，也更加了解每条指令的处理过程以及单周期CPU是如何工作的，同时本次实验也更加了解verilog语言，之前学的懵懵懂懂的，最重要的是学会模块化，将一项工作分成多个模块进行完成，先简化成小部分，然后再将其组合起来。</p>

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